The present invention relates to semiconductor processing. More specifically, the invention relates to a method and apparatus for forming dielectric films over high aspect ratio features at temperatures greater than about 500xc2x0 C., with the dielectric films having low moisture content and low shrinkage. Embodiments of the present invention are particularly useful to deposit doped dielectric films, such as borophosphosilicate glass (BPSG) films, borosilicate glass (BSG) films, or phosphosilicate glass (PSG) films, and to form ultra-shallow doped regions used, for example, as source/drain junctions or as channel stop diffusions in shallow trench isolation. In addition, embodiments of the present invention may also be used to deposit doped dielectric films used as premetal dielectric (PMD) layers, intermetal dielectric (IMD) layers, or other dielectric layers. Further embodiments of the present invention may further be used to deposit undoped dielectric films, such as undoped silicate glass (USG) films used as shallow trench isolation filling oxides, insulating layers, capping layers, or other layers.
One of the primary steps in fabricating modern semiconductor devices is forming a dielectric layer on a semiconductor substrate. As is well known, such a dielectric layer can be deposited by chemical vapor deposition (CVD). In a conventional thermal CVD process, reactive gases are supplied to the substrate surface where heat-induced chemical reactions (homogeneous or heterogeneous) take place to produce a desired film. In a conventional plasma process, a controlled plasma is formed to decompose and/or energize reactive species to produce the desired film. In general, reaction rates in thermal and plasma processes may be controlled by controlling one or more of the following: temperature, pressure, and reactant gas flow rate.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two-year/half-size rule (often called xe2x80x9cMoore""s Lawxe2x80x9d) which means that the number of devices which will fit on a chip doubles every two years. Today""s wafer fabrication plants are routinely producing 0.5 xcexcm and even 0.35 xcexcm feature size devices, and tomorrow""s plants soon will be producing devices having even smaller feature sizes. As device feature sizes become smaller and integration density increases, issues not previously considered crucial by the industry are becoming of greater concern. In particular, devices with increasingly high integration density have features with high (for example, greater than about 3:1 or 4:1) aspect ratios. (Aspect ratio is defined as the height-to-spacing ratio of two adjacent steps.)
Increasingly stringent requirements for processes in fabricating these high integration devices are needed in order to produce high quality devices, and conventional substrate processing systems are becoming inadequate to meeting these requirements. One requirement is that the dielectric films formed in the process of fabricating such devices need to be uniformly deposited over these high aspect ratio features without leaving substantial gaps or voids. Another requirement is that these films need to exhibit low shrinkage so that subsequent heating and/or wet etching steps do not cause voids to open up in the deposited film. However, conventional substrate processing systems that typically deposit dielectric films at temperatures less than about 450xc2x0 C. are unable to produce low moisture films having good gap-filling capabilities without opening substantial voids in subsequent heating and/or wet etching steps. As is well known, these gaps or voids may contribute to device performance unreliability and other problems. Dielectric films used, for example, as PMD or IMD layers in such devices need good high aspect ratio gap-fill capability to avoid problems caused by these gaps or voids. A further requirement is that metal contamination into the wafer during the processing steps be minimized to avoid short circuits and other problems in the devices. As is well known, conventional substrate processing systems using in situ plasma during processing experience physical sputtering of ions which attack chamber surfaces, such as aluminum walls, resulting in metal contamination of the substrate. Use of in situ plasma is therefore undesirable. An improved substrate processing system, which does not use in situ plasma, is needed to provide dielectric films with the desired characteristics of low moisture, high density, low shrinkage, good high aspect ratio gap-filling capability.
In addition to meeting these stringent requirements, substrate processing systems must be able to meet the higher demands for forming ultra-shallow doped regions, which are necessary for high integration devices with shrinking device geometries. With the advent of smaller device geometries, ultra-shallow doped regions in semiconductors are needed for various applications including, for example, source/drain junctions, channel stop diffusions for shallow trench isolation, etc. For example, MOS devices with channel lengths of less than 0.8 xcexcm often require source/drain junctions having depths less than about 250 nanometers (nm) for adequate device performance. For transistors separated by trench isolation structures of about 0.35 xcexcm depth, ultra-shallow channel stop regions having a depth on the order of hundreds of nm are usually required. For applications requiring ultra-shallow doped regions, it is important to provide uniform dopant distribution in the doped regions and good control of junction depth.
Current approaches to forming ultra-shallow doped regions, such as ion implantation and gaseous diffusion, are inadequate in some applications. With these current approaches, the ability to control dopant distribution and junction depth is limited, especially as the doped regions become shallower. With an approach like ion implantation, controlling dopant distribution is made difficult due to the built-up concentration of ions at the surface of the semiconductor material. Also, ion implantation causes damage to the semiconductor surface, and methods for repairing this substrate damage often make it more difficult to control dopant distribution and junction depth for ultra-shallow doped regions. For example, ions bombarded at relatively high energy levels have a tendency to tunnel or channel through the semiconductor material and cause damage such as point defects. These point defects, which may lead to irregular and nonuniform junction depths, may be fixed by annealing the implanted semiconductor material at high temperatures (greater than about 900xc2x0 C.). Annealing the implanted semiconductor material, however, may further increase the junction depth beyond that desired. With an approach like gaseous diffusion, controlling dopant distribution and junction depth is difficult to control in forming ultra-shallow doped regions. As technology progresses to even smaller geometry devices, an alternative approach that is able to control the dopant uniformity and junction depth in ultra-shallow doped regions is needed.
In forming ultra-shallow doped regions, one alternative approach to the current approaches of ion implantation and gaseous diffusion is the use of a doped dielectric film as a dopant diffusion source. In this alternative approach, a doped dielectric film is deposited onto a substrate and used as a source of dopants which are diffused into the substrate to form ultra-shallow doped regions. For example, doped dielectric films are deposited at temperatures less than 500xc2x0 C. in a deposition chamber, and subsequently heated at temperatures greater than 500xc2x0 C. in a different chamber, such as an annealing furnace, to perform the dopant diffusion to form the doped region. Controlling thickness, uniformity, and moisture content of the doped dielectric film is important in efficiently forming ultra-shallow doped junctions in the semiconductor material. Specifically, controlling the thickness and uniformity of the deposited doped dielectric film provides some control over the amount of dopants available for diffusion. Limiting the thickness of doped dielectric films used as diffusion sources also helps to increase wafer throughput by saving deposition (and subsequent etching) time. Moreover, a uniformly deposited film with even dopant uniformity can provide a more controlled diffusion of dopants from the film into the substrate. As is well known, moisture in doped dielectric films reacts with dopants to bind them in a crystal structure, resulting in fewer dopants available for diffusion into the substrate to form doped regions. It is desirable to use doped dielectric films having a low moisture content, since these films have more dopants available for use in the diffusion.
Several problems are encountered with conventional substrate processing systems when using a doped dielectric film as a dopant diffusion source. One problem is that it is difficult to obtain a high degree of control over film thickness and uniformity when using conventional systems to deposit the doped dielectric film. Another problem is that it is often difficult to ensure that adequate amounts of dopants in the doped dielectric film are available for diffusion into the substrate to form the ultra-shallow doped regions. A further problem is the existence of native oxides, which act as a barrier layer preventing dopants from diffusing into the substrate from the doped dielectric film, on substrate surfaces where the ultra-shallow doped regions are to be formed. These problems are discussed in further detail below.
Despite the advantages of using doped dielectric films as dopant diffusion sources to form ultra-shallow doped regions, the problem of being unable to control thickness and uniformity of the deposited doped dielectric film when using conventional deposition systems is of particular concern for two primary reasons. First, the inability to adequately control thickness and uniformity of the deposited doped dielectric film using conventional methods and apparatus undesirably results in a diminished ability to control the dopant uniformity and junction depth of the ultra-shallow doped region formed. For example, in a conventional sequential CVD chamber, a substrate rests on a belt and travels through various portions of the chamber. In each portion of the chamber, a layer having a certain thickness may be deposited. Thickness of the deposited film may be controlled by changing the belt speed, which provides limited control. Further, control over the thickness and dopant uniformity of the films deposited on different wafers is difficult when attempting to control film thickness and dopant concentration using belt speed. That is, the thicknesses of the deposited films on different wafers may vary and be unpredictable, leading to wafer-to-wafer unreliability. Second, being able to control the thickness of the deposited doped dielectric film, even for very thin films, is desirable for overall efficiency and increased wafer throughput. However, conventional approaches have only been capable of forming doped dielectric films with thicknesses on the order of thousands of Angstroms (xc3x85). Also, it may be difficult to maintain the thickness of the deposited film as thin as possible using systems relying on belt speed to control thickness of the deposited film. With thicker films deposited conventionally, some dopants may take longer to diffuse into the substrate, since they have greater distances to travel before reaching the semiconductor material. Also, removal of such a thick film used as a dopant diffusion source by etching or other technique often increases the total time to process the wafer. With growing pressures on manufacturers to improve efficiency, it is desirable to form the doped dielectric film as thin as possible in order to decrease the time needed to deposit and then remove the film. It is desirable to have a method and apparatus that can easily control the thickness and dopant uniformity of a doped dielectric film (less than about 500 xc3x85 thick at xc2x10.2 weight percentage dopant variation across the wafer) that is used as a dopant diffusion source.
Another problem with using doped dielectric films as dopant diffusion sources for ultra-shallow doped regions is that adequate amounts of dopants must be available for diffusion into the substrate. Films with high dopant concentration are often needed to provide adequate amounts of dopants for uniform diffusion into the substrate to form ultra-shallow junctions. However, moisture absorption and outgassing are two problems relating to adequate dopant availability. Doped dielectric films, especially those with high dopant concentrations, tend to absorb moisture shortly after a wafer is exposed to ambient moisture in a clean room (e.g. when the wafer is transferred from the deposition chamber after deposition of the doped dielectric film to a different processing chamber for the next processing step in a multiple-step process). The absorbed moisture (H2O) then reacts with the dopants in the dielectric film, causing the film to crystallize. Due to the crystal structure binding the dopants within the film, these dopants become unavailable for diffusion into the substrate, even after a subsequent heating of the wafer by rapid thermal processing or annealing in another chamber. Moisture absorption thus reduces the amount of dopants for diffusion into the substrate. In addition to the moisture absorption problem, outgassing of dopants from the doped dielectric film also may occur in subsequent heating steps. These dopants diffuse out of the film away from the substrate, resulting in fewer dopants available to be diffused into the substrate to form ultra-shallow doped regions.
Even if adequate dopants are available for diffusion, the problem of native oxides remains an important consideration when using doped dielectric films as diffusion sources. Native oxides existing on the substrate surface where ultra-shallow doped regions are to be formed prevent effective and uniform dopant diffusion into the silicon. Therefore, native oxides, which act as a diffusion barrier layer to the dopants, need to be removed. Removing native oxides has been done using conventional techniques such as wet etching using liquid etchants, and dry etching using an in situ plasma. However, using liquid etchants is often difficult to control and may result in overetching the substrate. Substrates that have native oxides cleaned by conventional methods such as wet etching have shelf lives of less than about one week before native oxides begin to form again, making it desirable to process the wafers shortly after the native oxides have been removed. Using dry etching to remove native oxides with an in situ plasma results in plasma damage to the surface of the substrate. In addition to causing surface plasma damage, in situ plasma dry etching may undesirably result in more metal contamination, as discussed earlier. Accordingly, it is important to efficiently remove native oxides without damaging the substrate surface so dopants may diffuse into the substrate uniformly for ultra-shallow doped regions.
In addition to providing dense, low moisture dielectric films having uniform thickness and high aspect ratio gap-filling capability with low metal contamination, improved quality and overall efficiency in fabricating integrated circuit devices is also important. An important way to improve quality and overall efficiency in fabricating devices is to clean the chamber effectively and economically. With growing pressures on manufacturers to improve processing quality and overall efficiency, eliminating the total down-time in a multiple-step process without compromising the quality of the wafers has become increasingly important for saving both time and money. During CVD processing, reactive gases released inside the processing chamber form layers such as silicon oxides or nitrides on the surface of a substrate being processed. Undesirable oxide deposition occurs elsewhere in the CVD apparatus, such as in the area between the gas mixing box and gas distribution manifold. Undesired oxide residues also may be deposited in or around the exhaust channel and the walls of the processing chamber during such CVD processes. Over time, failure to clean the residue from the CVD apparatus often results in degraded, unreliable processes and defective substrates. Without frequent cleaning procedures, impurities from the residue built up in the CVD apparatus can migrate onto the substrate. The problem of impurities causing damage to the devices on the substrate is of particular concern with today""s increasingly small device dimensions. Thus, CVD system maintenance is important for the smooth operation of substrate processing, as well as resulting in improved device yield and better product performance.
Frequently, periodic chamber cleanings between processing of every N wafers is needed to improve CVD system performance in producing high quality devices. Providing an efficient, non-damaging clean of the chamber and/or substrate is often able to enhance performance and quality of the devices produced. In addition to improving the quality of the above-discussed chamber cleanings (which are done without breaking the vacuum seal), preventive maintenance chamber cleanings (where the vacuum seal is broken by opening the chamber lid to physically wipe down the chamber) are performed between multiple periodic chamber cleanings. Often, performing the necessary preventive maintenance chamber cleanings involves opening the chamber lid and any other chamber parts that might obstruct the lid, which is a time-consuming procedure that interferes with normal production processing.
In light of the above, improved methods, systems and apparatus are needed for depositing dense, low moisture dielectric films with uniform thicknesses and high aspect ratio gap-filling capabilities. Optimally, these improved methods and apparatus will also provide a chamber clean with low metal contamination. Improved methods and apparatus are also needed for forming doped dielectric films as dopant diffusion sources for ultra-shallow junctions. These methods and apparatus should be capable of efficiently removing native oxides to ensure effective and uniform dopant diffusion from the doped dielectric layer without causing significant surface damage to the silicon wafer. Further, for some applications it is desirable to provide multiple deposition and cleaning capabilities in a single chamber with a simplified design to minimize the time consumed for different types of cleanings. What is needed, therefore, are systems and methods that are capable of high quality, efficient, high temperature deposition and efficient, gentle cleaning. In particular, these systems and methods should be designed to be compatible with processing requirements for forming devices with high aspect ratio features, and for forming ultra-shallow doped regions.
The present invention provides systems, methods and apparatus for high temperature (at least about 500-800xc2x0 C.) processing of semiconductor wafers. Embodiments of the present invention include systems, methods and apparatus which enable multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing to produce high integration devices having high aspect ratio features. Performing multiple process steps in the same chamber also increases the control over process parameters, substantially reduces moisture content in deposited films, and minimizes device damage due to metal contamination or process residue contamination.
In particular, the present invention provides high temperature deposition, heating and efficient cleaning for forming dielectric films having relatively thin film thicknesses. Embodiments of the present invention are particularly useful to deposit doped dielectric films, such as borophosphosilicate glass (BPSG) films, borosilicate glass (BSG) films, or phosphosilicate glass (PSG) films, and to form an ultra-shallow doped region used, for example, as source/drain junctions or as channel stop diffusions in shallow trench isolation. In addition, embodiments of the present invention may also be used to deposit doped dielectric films used as premetal dielectric (PMD) layers, intermetal dielectric (IMD) layers, or other dielectric layers. Further embodiments of the present invention may further be used to deposit undoped dielectric films used as shallow trench isolation filling oxides, insulating layers, capping layers, or other layers.
Methods according to the present invention include depositing dielectric films by CVD on a substrate in a vacuum chamber having a pressure between about 10-760 torr, and heating the substrate to a temperature greater than about 500xc2x0 C. The substrate may be heated for a variety of purposes, such as performing reflow of deposited dielectric layers for planarization, or for driving in dopants from a deposited doped dielectric layer. The process may be carried out in a single step (e.g., depositing and reflowing the film on the wafer at temperatures greater than 500xc2x0 C.), or in multiple steps (e.g., depositing the film on the wafer at temperatures less than 500xc2x0 C. and then heating the film on the wafer after the film has been deposited). In either case, high temperature processing is accomplished without removing the wafer from the vacuum chamber, which advantageously reduces moisture absorption in the dielectric film. The high temperature processing also enables in situ deposition of doped dielectric films with capping layers to advantageously reduce outgassing of dopants from the doped film and lower moisture content. In a specific embodiment, reactive gases are delivered to the substrate surface, where heat-induced chemical reactions take place to produce the dielectric film. Additionally or alternatively, a controlled plasma may be formed to facilitate the decomposition of the reactive species.
In an exemplary embodiment, the dielectric film is a thin doped film used as a dopant diffusion source for an ultra-shallow junction. The film is deposited at temperatures greater than about 500xc2x0 C. onto the substrate and heated to higher temperatures, usually greater than 600xc2x0 C. and preferably greater than about 700xc2x0 C., to diffuse dopants from the dielectric layer to the underlying substrate. Performing the deposition and heating steps in the same chamber provides better control of the thickness, uniformity, and moisture content of the doped dielectric film. Improving the moisture content of the film increases the amounts of available dopants in the film, which is particularly advantageous for forming ultra-shallow junctions in high integration devices.
In another aspect of the invention, a remote plasma system is provided for etching undesired deposits on the inner walls of the vacuum chamber and components of the apparatus, and for cleaning native oxides and other residue from the semiconductor wafer prior to processing. A gentle cleaning technique using a remote energy source is preferably employed instead of a conventional in situ plasma process to lower metal contamination. For example, the remote plasma system provides a remote plasma and preferably fluorine radicals from the plasma are able to enter the chamber, which is at high temperatures, and provide a gentle, thermal cleaning of the chamber. With the remote plasma system, only chemical reactions are utilized and the problem of physical sputtering effects are eliminated. In contrast, with the use of an in situ plasma system, sputtering effects attack aluminum chamber walls, which may then lead to metal contamination in the processed wafer. In the thermal cleaning process using the remote plasma system, the radicals directed into the chamber can effectively clean unwanted deposits and residues from the surfaces in the chamber while the plasma remains remote or exterior to the chamber. Another advantage of the remote plasma system is that native oxides can be efficiently removed from the wafer to effectively ensure effective and uniform dopant diffusion from the doped dielectric layer without causing significant surface damage to the silicon wafer. A further advantage of the remote plasma system is that the system may also be configured for use to deposit films by using different input gases as needed.
In a preferred embodiment, the remote plasma cleaning system is a microwave plasma system configured to produce and deliver a select species (such as fluorine, chlorine or other radicals) to the processing chamber. The remote plasma system energizes gases by microwave radiation to create a plasma with etching radicals. Specifically, microwaves are created by a magnetron or other suitable energy source and directed through a waveguide system to an applicator tube, where a plasma is created. Reactive gases are then fed into the applicator tube and energized by the microwave energy, which sustains the ionization of the ignited plasma to produce a flow of radicals into the processing chamber. For cleaning, the radicals interact with residue formed on the chamber walls to form reactant gases that are suitably discharged form the chamber by an exhaust system. The microwave plasma system may also be adapted to deposit plasma enhanced CVD films by delivering deposition reactive gases into the processing chamber.
In another aspect of the invention, the remote plasma system includes an endpoint detection system for indicating when the chamber cleaning has concluded. The lack of plasma in the chamber can make it difficult, using conventional endpoint detection systems, to pinpoint the time at which the cleaning has been completed (i.e., when the last process gas residue in the chamber has reacted with the cleaning etchant so that it can be discharged from the chamber). This is because conventional endpoint detection systems typically rely on the use of a plasma within the chamber to check emissions from the in situ plasma to determine the end of the cleaning process. In the present invention, an endpoint detection assembly is coupled to the gas outlet of the processing chamber to determine the endpoint of the cleaning process by detecting changes in light intensity that occur due to absorbance of light by the exhausted clean gas reactants, such as SiF4.
In yet another aspect of the present invention, a method provides gettering of any adsorbed clean gases, such as fluorine, from the surface of chamber walls. According to the present invention, a first cleaning gas containing fluorine is introduced into the processing chamber to clean the processing chamber of deposition residue. A second cleaning gas is then introduced into the processing chamber after the residue has been removed with the first cleaning gas. The second cleaning gas removes cleaning residue formed by the reaction between the first cleaning gas and the interior surfaces of the processing chamber. Removing or gettering the cleaning residue from the chamber provides a number of advantages. For example, in a preferred embodiment of the present invention, fluorine radicals are delivered into the processing chamber to remove residue, such as silicon oxide, by forming a silicon-fluoride gas product which is pumped away from chamber. After the fluorine-based chamber cleaning procedure, any adsorbed fluorine on the surface of the chamber walls which might otherwise interact with, or be incorporated into, the deposited film on the next wafer to be processed is gettered. In an alternative embodiment, the gettering may be performed by seasoning the chamber using microwave-generated atomic oxygen and a silicon source to deposit a thin film of oxide onto the chamber to trap any adsorbed fluorine and prevent contamination of the subsequently deposited films.
The present invention also provides various heat-resistant and process-compatible components for high temperature processing. The system of the present invention includes a vapor deposition apparatus having an enclosure assembly housing a processing chamber. The apparatus includes a heating assembly having a pedestal/heater for heating the wafer to temperatures up to about 500-800xc2x0 C. The pedestal preferably comprises a material that is substantially resistant to reactions with the process gases and to deposition by the process gases at temperatures of at least about 400xc2x0 C., and preferably at temperatures up to about 500-800xc2x0 C. In addition, the pedestal preferably comprises a material that is substantially resistant to etching at high temperatures (i.e., 500-800xc2x0 C.) by the fluorine radicals introduced into the chamber during cleaning. In an exemplary embodiment, the pedestal/heater comprises a resistive heating element imbedded in a ceramic material, such as aluminum oxide or preferably aluminum nitride.
The heating assembly of the present invention further includes a support shaft for supporting the pedestal/heater within the chamber and for housing the necessary electrical connections thereto. The support shaft preferably comprises a ceramic material that is diffusion-bonded to the pedestal/heater to provide a vacuum seal within the shaft. This vacuum seal allows the hollow interior of the shaft to be maintained at ambient temperature and pressure during high temperature processing, which protects the electrodes and other electrical connections from corrosion from the process and clean gases within the chamber. In addition, providing ambient pressure within the shaft minimizes arcing from the power source through the hollow core of the shaft to power leads or the outer walls of the shaft.
In still another aspect of the invention, a chamber liner is provided around the pedestal/heater to insulate the chamber walls from the heater. Preferably, the chamber liner includes an inner portion comprised of a material such as ceramic that is resistant to high temperatures and to deposition/clean reactions, and an outer portion comprised of a material resistant to cracking. The inner portion of the liner insulates the chamber walls to reduce the wafer edge cooling effects which might otherwise adversely affect deposited film uniformity. The outer portion of the chamber liner is substantially thicker than the inner portion to bridge the gap between the wafer and the walls, while minimizing cracking which might otherwise occur with a single, relatively thick ceramic liner. In an exemplary embodiment, the outer portion of the liner includes air gaps to increase the insulation provided by the liner.
In still a further aspect of the invention, a lid assembly is provided for the enclosure assembly. The lid assembly includes a gas mixing block (or box) coupled to one or more clean gas passages and one or more process gas passages for receiving process and clean gases and for delivering these gases into the chamber. One or more valves are provided on either the clean gas passages or the process gas passages to selectively allow gas to flow through to the gas mixing block. This embodiment facilitates the in situ cleaning method of the present invention by allowing the apparatus to quickly and efficiently switch between processing and cleaning, which increases the throughput of the system.
In an-exemplary embodiment, the lid assembly further includes a base plate having a gas inlet for receiving one or more gases and a gas distribution plate including a plurality of holes for dispersing the gases into the processing chamber. The lid assembly includes one or more bypass passages in the base plate that offer less resistance to fluid flow than the gas distribution holes. During cleaning, for example, at least a portion of the cleaning gases will pass through the bypass passages directly into the chamber to increase the speed of the cleaning process, thereby decreasing the down time of the chamber. The apparatus preferably includes a control system, such as a valve and a controller, for partially or completely closing the bypass passages to control the gas flow through the gas distribution holes.
These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached figures.